A User’s and Hacker’s Guide to the SimpleScalar Architectural Research Tool Set

A User’s and Hacker’s Guide to the
SimpleScalar Architectural Research
Tool Set
M
(for tool set release 2.0)
R
Todd M. Austin
L
taustin@ichips.intel.com
Intel MicroComputer Research Labs
January, 1997
Todd M. Austin
Page 1

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Tutorial Overview
•
Computer Architecture Simulation Primer
•
SimpleScalar Tool Set
q Overview
q User’s Guide
•
SimpleScalar Instruction Set Architecture
•
Out-of-Order Issue Simulator
q Model Microarchitecture
q Implementation Details
•
Hacking SimpleScalar
•
Looking Ahead
Todd M. Austin
Page 2

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A Computer Architecture Simulator Primer
•
What is an architectural simulator?
q a tool that reproduces the behavior of a computing device
System
Device
System Outputs
Inputs
Simulator
System Metrics
•
Why use a simulator?
q leverage faster, more flexible S/W development cycle
q permits more design space exploration
q facilitates validation before H/W becomes available
q level of abstraction can be throttled to design task
q possible to increase/improve system instrumentation
Todd M. Austin
Page 3

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A Taxonomy of Simulation Tools
Architectural Simulators
Functional
Performance
Trace-Driven
Exec-Driven
Inst Schedulers
Cycle Timers
Interpreters
Direct Execution
•
shaded tools are included in the SimpleScalar tool set
Todd M. Austin
Page 4

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Functional vs. Performance Simulators
n
o
Arch
uArch
f
i
c
a
ti
Development
eci
Spec
Spec
p
S
on
ti
Arch
uArch
la
u
m
Sim
Sim
Si
•
functional simulators implement the architecture
q the architecture is what programmer’s see
•
performance simulators implement the microarchitecture
q model system internals (microarchitecture)
q often concerned with time
Todd M. Austin
Page 5

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Execution- vs. Trace-Driven Simulation
•
trace-based simulation:
inst trace
Simulator
q simulator reads a “trace” of inst captured during a previous execution
q easiest to implement, no functional component needed
•
execution-driven simulation:
program
Simulator
q simulator “runs” the program, generating a trace on-the-fly
q more difficult to implement, but has many advantages
q direct-execution: instrumented program runs on host
Todd M. Austin
Page 6

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Instruction Schedulers vs. Cycle Timers
•
constraint-based instruction schedulers
q simulator schedules instructions into execution graph based on
availability of microarchitecture resources
q instructions are handled one-at-a-time and in order
q simpler to modify, but usually less detailed
•
cycle-timer simulators
q simulator tracks microarchitecture state for each cycle
q many instructions may be “in flight” at any time
q simulator state == state of the microarchitecture
q perfect for detailed microarchitecture simulation, simulator faithfully
tracks microarchitecture function
Todd M. Austin
Page 7

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The Zen of Simulator Design
Performance
Performance: speeds design cycle
Flexibility: maximizes design scope
Pick
Two
Detail: minimizes risk
Detail
Flexibility
•
design goals will drive which aspects are optimized
•
The SimpleScalar Architectural Research Tool Set
q optimizes performance and flexibility
q in addition, provides portability and varied detail
Todd M. Austin
Page 8

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Tutorial Overview
•
Computer Architecture Simulation Primer
•
SimpleScalar Tool Set
q Overview
q User’s Guide
•
SimpleScalar Instruction Set Architecture
•
Out-of-Order Issue Simulator
q Model Microarchitecture
q Implementation Details
•
Hacking SimpleScalar
•
Looking Ahead
Todd M. Austin
Page 9

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The SimpleScalar Tool Set
•
computer architecture research test bed
q compilers, assembler, linker, libraries, and simulators
q targeted to the virtual SimpleScalar architecture
q hosted on most any Unix-like machine
•
developed during my dissertation work at UW-Madison
q third generation simulation system (Sohi → Franklin → Austin)
q 2.5 years to develop this incarnation
q first public release in July ‘96, made with Doug Burger
q second public release in January ‘97
•
freely available with source and docs from UW-Madison
http://www.cs.wisc.edu/~mscalar/simplescalar.html
Todd M. Austin
Page 10

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